Search for: All records

This paper presents a technique for achieving spatially targeted neural stimulation with suppression of driver nonideality-induced common-mode (CM) artifact in low-latency closed-loop neuromodulation applications. The proposed approach utilizes computationally guided concurrent stimulation across multiple electrodes to achieve spatial selectivity in stimulation. The proposed architecture supports flexible storage of multiple, precomputed vector stimulation patterns in integrated memory. A selected stimulation pattern can be quickly accessed and administered in response to decoded neural activity. Additionally, a combination of the stimulator circuit architecture and mixed-signal current imbalance compensation techniques effectively suppress CM artifacts to below 50 mV. These techniques are demonstrated in a 180 nm HV CMOS test-chip containing 46 stimulation drivers of 26 V compliance and validated through a combination of bench, saline, and in vivo tests.